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	<title>Boolean Algebra - Revision history</title>
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		<title>Digimer: Created page with &#039;{{header}}  &#039;&#039;&#039; Boolean Algebra &#039;&#039;&#039;  These are the various &#039;logic gates&#039; used to create all computer logic. At their core, they are all made up of the &#039;NAND&#039; gate.  = Logic Gates…&#039;</title>
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		<updated>2009-10-11T08:12:18Z</updated>

		<summary type="html">&lt;p&gt;Created page with &amp;#039;{{header}}  &amp;#039;&amp;#039;&amp;#039; Boolean Algebra &amp;#039;&amp;#039;&amp;#039;  These are the various &amp;#039;logic gates&amp;#039; used to create all computer logic. At their core, they are all made up of the &amp;#039;NAND&amp;#039; gate.  = Logic Gates…&amp;#039;&lt;/p&gt;
&lt;p&gt;&lt;b&gt;Páàjì titun&lt;/b&gt;&lt;/p&gt;&lt;div&gt;{{header}}&lt;br /&gt;
&lt;br /&gt;
&amp;#039;&amp;#039;&amp;#039; Boolean Algebra &amp;#039;&amp;#039;&amp;#039;&lt;br /&gt;
&lt;br /&gt;
These are the various &amp;#039;logic gates&amp;#039; used to create all computer logic. At their core, they are all made up of the &amp;#039;NAND&amp;#039; gate.&lt;br /&gt;
&lt;br /&gt;
= Logic Gates =&lt;br /&gt;
&lt;br /&gt;
: Logic gates can be represented by showing two input lines and one output line followed by a table showing what electrical/[[binary]] state the inputs must be in to effect a certain output state. In these &amp;#039;Truth Tables&amp;#039;, the two inputs are represented as inputs &amp;#039;A&amp;#039; and &amp;#039;B&amp;#039;, and the output is represented by &amp;#039;Y&amp;#039;.&lt;br /&gt;
&lt;br /&gt;
: In real terms, a signal state of &amp;quot;true&amp;quot; is achieved when the voltage on the line goes above a certain threshold voltage and can be represented as a binary &amp;#039;1&amp;#039; or described as being &amp;#039;high&amp;#039;. Conversely, a signal state of &amp;quot;false&amp;quot; is achieved when the voltage on the line goes below a certain threshold voltage and can be represented as a binary &amp;#039;0&amp;#039; or described as being &amp;#039;low&amp;#039;. &lt;br /&gt;
&lt;br /&gt;
A note of interest; Logic gates use a buffer space between the voltage states needed to determine a high or low state. This is the case so that slight variances in the line voltage won&amp;#039;t change the value of line. For example, a 5 volt gate may require that the line voltage goes above 3.5 volts before a low signal is declared high. In turn, the signal will not go low again until the voltage drops to below 1.5 volts. This way, a small spike above 1.5 volts when the signal is low will not change it&amp;#039;s value to high and a slight voltage dip below 3.5 volts will not drop a high signal to low.&lt;br /&gt;
&lt;br /&gt;
== AND ==&lt;br /&gt;
&lt;br /&gt;
: A &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;and&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039; B must be true (1) for the output to be true (1). If either input is false (0), the output becomes (0).&lt;br /&gt;
&lt;br /&gt;
* Truth Table&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | A | B || Y |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | 0 | 0 || 0 |&lt;br /&gt;
  | 0 | 1 || 0 |&lt;br /&gt;
  | 1 | 0 || 0 |&lt;br /&gt;
  | 1 | 1 || 1 |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
&lt;br /&gt;
== NAND ==&lt;br /&gt;
&lt;br /&gt;
* (Not AND)&lt;br /&gt;
&lt;br /&gt;
: A &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;and&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039; B may &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;not&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039; both be true (1) for the output to be true (1). If either input is false (0), the output becomes (1). This is in direct opposition to the &amp;#039;AND&amp;#039; gate.&lt;br /&gt;
&lt;br /&gt;
* Truth Table&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | A | B || Y |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | 0 | 0 || 1 |&lt;br /&gt;
  | 0 | 1 || 1 |&lt;br /&gt;
  | 1 | 0 || 1 |&lt;br /&gt;
  | 1 | 1 || 0 |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
&lt;br /&gt;
== OR ==&lt;br /&gt;
&lt;br /&gt;
: If A &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;or&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039; B is true (1), the output becomes true (1).&lt;br /&gt;
&lt;br /&gt;
* Truth Table&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | A | B || Y |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | 0 | 0 || 0 |&lt;br /&gt;
  | 0 | 1 || 1 |&lt;br /&gt;
  | 1 | 0 || 1 |&lt;br /&gt;
  | 1 | 1 || 1 |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
&lt;br /&gt;
== NOR ==&lt;br /&gt;
&lt;br /&gt;
* (Not OR)&lt;br /&gt;
&lt;br /&gt;
: When A &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;nor&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039; B is true (1), the output will become true (1). This is in direct opposition to the &amp;#039;OR&amp;#039; gate.&lt;br /&gt;
&lt;br /&gt;
* Truth Table&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | A | B || Y |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | 0 | 0 || 1 |&lt;br /&gt;
  | 0 | 1 || 0 |&lt;br /&gt;
  | 1 | 0 || 0 |&lt;br /&gt;
  | 1 | 1 || 0 |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
&lt;br /&gt;
== XOR ==&lt;br /&gt;
&lt;br /&gt;
* (eXclusive OR)&lt;br /&gt;
&lt;br /&gt;
: If A &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;or&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039; B is true (1) &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;exclusively&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;, the output becomes true (1). If both A and B become true, the output returns to &amp;#039;0&amp;#039;.&lt;br /&gt;
&lt;br /&gt;
* Truth Table&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | A | B || Y |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | 0 | 0 || 0 |&lt;br /&gt;
  | 0 | 1 || 1 |&lt;br /&gt;
  | 1 | 0 || 1 |&lt;br /&gt;
  | 1 | 1 || 0 |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
&lt;br /&gt;
== XNOR ==&lt;br /&gt;
&lt;br /&gt;
* (eXclusive Not OR)&lt;br /&gt;
&lt;br /&gt;
: If A &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;nor&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039; B is true (1) &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;exclusively&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;, the output becomes true (1). This is in direct opposition to the &amp;#039;XOR&amp;#039; gate.&lt;br /&gt;
&lt;br /&gt;
* Truth Table&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | A | B || Y |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
  | 0 | 0 || 1 |&lt;br /&gt;
  | 0 | 1 || 0 |&lt;br /&gt;
  | 1 | 0 || 0 |&lt;br /&gt;
  | 1 | 1 || 1 |&lt;br /&gt;
  +---+---++---+&lt;br /&gt;
&lt;br /&gt;
== Inverter ==&lt;br /&gt;
&lt;br /&gt;
: Though not a typical logic gate, it is a very important gate just the same. It&amp;#039;s purpose is to &amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039;invert&amp;#039;&amp;#039;&amp;#039;&amp;#039;&amp;#039; the input signal. So, if the input line is &amp;#039;true&amp;#039;, the output becomes &amp;#039;false&amp;#039;, and vice versa.&lt;br /&gt;
&lt;br /&gt;
* Truth Table&lt;br /&gt;
  +---++---+&lt;br /&gt;
  | A || Y |&lt;br /&gt;
  +---++---+&lt;br /&gt;
  | 0 || 1 |&lt;br /&gt;
  | 1 || 0 |&lt;br /&gt;
  +---++---+&lt;br /&gt;
&lt;br /&gt;
{{footer}}&lt;/div&gt;</summary>
		<author><name>Digimer</name></author>
	</entry>
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